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Adding XADC to Zynq DeviceTree

Question asked by Quamstar on Jan 12, 2017
Latest reply on Jan 13, 2017 by larsc
Branched from an earlier discussion

Hi Lars,


i'm working on a similar issue and trying to implement the xadc into the reference design for system monitoring of external signals. Therefore i need to add all aux(0:16) channels to the design. For now, I figured out that the iio driver provided by ADI are already using the xadc drivers and there are some modification in the devictree and system design required. Taking a look into the hdl-design, there are no implementation of any xadc headers pins for the zc702 and zc706. As you mentioned the VN/VP (channel 0) is alway connected, i could not find anythin in the system constraint or system_top files. There is only a entry for fot XADC GPIO. 


Since, the ZC702 has a dedicated routing of the AUX0 and AUX8 channel, do i only need to insert those into the system constraint and modify the gpio_bd width (currently inout [15:0] gpio_bd) or is there something else to update?


Do someone has experience by insert the XADC wizard IP into the reference design?


Thanks and regards