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Clock limitations on AD9528 not clear

Question asked by htorke on Jan 9, 2017
Latest reply on Jan 10, 2017 by sripad
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In this document: https://ez.analog.com/docs/DOC-16454

 

It is listed with the following requirements:

 

• The PLL2 VCO frequency operates in range from 3450MHz to 4025MHz.

 

• Maximum frequency after the RF VCO divider (M1) is limited to 1000MHz.

 

However in the examples given, such as example 1, VCO is set to 3686.4 and M1 is set to 3. This would make the frequency after the RF VCO divider 1228.8, which should be violating that second rule. However, it is stated that that combination is acceptable, indicating that it is fine to exceed 1000 MHz.

 

Further, the RF VCO divider has listed values of /2, /3, and /4, however the datasheet lists the available divisions as /3,  /4, and /5. In general, if a /3 divider is used on a VCO operating in the range of 3450 to 4025 MHz, the resultant frequency should ALWAYS exceed 1000 MHz, making the /3 divider useless if that constraint exists.

 

Can you clarify what the limitations for this chip's settings are?

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