According to the CCES help files, copying apt-sc589.c file to your project and modifying the memory page entries will modify the start routines of the MMU to configure the different memory ranges as required for a projects particular requirements. For example, I wish to change a range of L2 SRAM so that it is uncached instead of cached:
0x20088000u, 0x2009FFFFu, ADI_MMU_WB_CACHED
So, I modified the above entry to look like this:
0x20088000u, 0x2009FFFFu, ADI_MMU_RW_UNCACHED
I then located a simple structure to this memory location for the exchange of data across all 3 cores. This worked perfectly on the ezkit evaluation board running silicon rev. 0.1. However, we have finally received production silicon rev 1.0, and this appears to not work. If I compile for silicon rev "any", this works even on the Rev 1.0 silicon.
I seems like I have missed something, or there is an issue with the compiler. Any insight?