In AD9371 evaluation board, AD9528 uses 30.72MHz as the reference clock to generate 122.88MHz DEV_CLK. Can AD9528 use 26MHz as the reference clock instead of 30.72MHz to generate the required DEV_CLK of AD9371?
AD9528 is an integer-N PLL , hence you cannot use 26MHz as reference.
In Evaluation board , with 122.88 default crystal there are limitation for generating desired DEV_CLK, same is explained in below document. Document also explains how to overcome this limitation by changing the Crystal.
Thanks for the reply.
30.72MHz x 4=122.88MHz, if I choose AD9528 VCXO as 26 x 5=130MHz and use the following formula
VCO freq=VCXO freq x M1 x N2 /(R1)=130 x 3 x 30/(3)=3900MHz //between 3450MHz to 4025MHz
DEV_CLK freq= VCO freq/(M1*chDIV)=3900/(3 x 5)=260MHz
Can this work for AD9371 or AD9528?
Above configuration will Work.
26 MHz Reference , VCXO 130 MHz, DEV_CLK - 260 MHz.
What is your target datarate ?
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