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AD7764 timings

Question asked by abhijitpethkar on Sep 8, 2011
Latest reply on Sep 12, 2011 by MClifford

Dear Friends,


I am having some questions regarding the timing of AD7764 ADC


1. If I am supposed to measure the FILTER-SETTLE bit on a oscilloscope then should I assume that once all the 32 bits of data are inside the

buffer (ready to be read) and in the next cycle of MCLK (rising edge) the FILTER-SETTLE bit goes high.

2. In other words what is the time between the FILTER-SETTLE bit going high and the FSO# signal getting aserted (going low)?

3. Is there any relationship between the SYNC# signal and the FSI# signal? In other words can we assert the FSI signal and the SYNC# signal at

the same time?

4. After RESET# signal is asserted what is the time delay to be given for the FSI# signal to be asserted?


5. We want to use the AD7764 for continuously sampling the incoming data. As per the datasheet for receiving the digital data from the ADC we


have to synchronise with SYNC# signal and after some specified time we can get the data. We would like to know


i) If suppose we give the SYNC# signal and the input analog signal is not present then also the ADC will continously give the digital output. Do we


have to assert SYNC# signal everytime for getting the data continously from the ADC?


Kindly revert



Abhijit Pethkar