In my design two AD7763 are sharing the same SPI bus, as described at page 15 of the AD7763 datasheet (rev. B). I do have some question regarding the shared I/O:
- Are the SCO connected together? If so, which ADC generates the SCO signal?
- Are DRDY_N supposed to be tied up as well?
- The datasheet specify that also FSO can be tied together (page 17). The logic analyzed reveals a conflict though. Is this correct?
Board configuration: MCLK of 5MHz (connected to both ADCs) and CDIV = 0, SCR = 1, SCR = 1.
ADC1: SH[2:0] = 1, ADDR[2:0] = 0
ADC1: SH[2:0] = 1, ADDR[2:0] = 1
In the attached screenshots, both ADCs are sending back data through the SDO, but they are not properly synchronized. Therefore SDO would have conflicts (as at time 4us in the image). MCLK, SCO, SDI, FSI are shared between ADCs.
Could you give me some hints?