I have a board with AD1974 configured via SPI by microcontroller. Problem is that once per 6-7 initializations the AD1974 start in standalone mode, which is not the desired configuration - I see distorted levels on LRCLK and BCLK when COUT data is high. The microcontroller uses following startup procedure:
1.Hold the RESET low.
2.Set CLATCH for all SPI slaves to high.
3.Release the RESET to high.
4.Setup the onboard DSP - it provide MCLK to AD1974.
5.Setup AD1974 registers to desired values.
There are some delays between the steps, but I suspect some of time times is not met.
A look trough datasheet, but such timings are not clearly stated:
Time around RESET state where CLATCH must be high to avoid standalone mode.
Is it any relation with MCLK signal to be valid and standalone mode.
Is it required any timeout after RESET or valid MCLK before to write to configuration registers.