New with DDS, I have AD9956 Eval board.
I load the profile frequency, but when I read it back it turns all to zero.
Why ? and how can I fix this ?
Just to check, are you successful in getting your desired output frequency from the board?
So you mention that it is normal to receive all zero from reading freq profiles from DDS
if we get desired output frequency from DDS,
We get no output frequency
If you are getting all 0's back on readback then the device is not registering your effort to program it for some reason. Have you sent an I/O UPDATE signal?
Yes I send I/O Update. (Automatic update is also selected)
1 master (No Slave) with 2 wire serial com.
With Fractional Divider I want to generate 2.4GHz Signal
24.576 MHz Xtal is connected & Xtal is selected.
What may be the possible missing ?
Software is up and running with Green color connected and master.
It looks like DDS is hold in Reset mode,
What to do ?
It will help us to diagnose this if you can share your programming instructions for the device and a readback datadump from all the registers after you have attempted to program it.
Under Control Menu:
Ref Clock: 2400 MHz (Comes from onboard VCO)
Divider Ratio : 8
System Clock : 300 MHz
None of the parameters are checked.
Under Clock Driver Control, Charge Pump Menu:
Clock Driver item > RF Divider Output is checked
Use Internal Rset is checked
Added rising surge current is 7.60mA
Added falling surge current is 4.05 mA
Phase Frequency detector / Charge Pump > Enable Crystal Oscillator is cheked (Onboard 25 MHz Crystal)
Charge Pump Polarity > GND referenced VCO is selected
Divider N > Bypassed
Divider M > Bypassed
PLL Lock Detect > Enabled
PLL Lock Mode > Lock Detect
Under Profile Menu:
Profile 0 is active and Output frequency is 24.999 MHz (When we write 25 MHz it turns to be like that)
So we hope to receive single tone at 24.99 MHz from PLL output
where J6 output is fed to J3 PLL osc input
I suppose there is onboard 25 MHz Crystal on J2 PLL ref input
Under DUT Signals Menu
Master Auto I/O Update is selected
So we just load the parameters but when we read for example profile frequencies they all turn back to zero, meanwhile there is no output in spectrum analyzer.
That is also the same for Debug window.
We "write" registers but they all turn back to zero when we read them.
It looks DDS is always keeping in Reset mode !!!
To sum up:
We want to generate 2.4-2.5 GHz RF signal at VCO output.
J16 is connnected to J1 to supply RF Diveder set to 8.
So we try to get DDS sysclock is 300 MHz.
From DDS we want to get 25 MHz at J6.
J6 is fed to J3, where J2 is empty now (I have tried external 25 MHz also from here)
All voltage supplies seems to be OK.
What would be the problem, can you help me ?
It seems that the root cause of this is that the DDS doesn't latch up the register values when you write using SPI. This was verified when you readback a frequency profile register, with a value written in it, and still reads a zero value.It's as if it wasn't set by the software. Now just an extra validation, can you do a readback on CFR2 (Control Function Register 2). It has a 0x00007800 default value so you don't need to write the register before doing a readback. If you're still getting all zeroes then there is something wrong in the SPI. Can you also check the RESET and SYNC_IO if they are not floating and are in low logic during the operation of the board. In addition, when you attached the crystal, were R57 and R58 populated with zero ohm resistors?
I am using the onborad X1 XTAL with R57 and R58 populated with zero ohm resistors in its original form.
We did not make any change on it but I checked that the zero ohm resistors are populated as you mentioned.
I am trying to program DDS Eval Board with VCO from PC where all jumpers are at correct position.
Operating system of my PC is Windows 10 but I have checked to make the software to work compatible with Windows XP as administrator.
I have read CFR2 (Control Function Register 2) as 0X000078FF07 instead of 0X0000780007
I can see that I can send Reset Master signal (3.3V) from the Debug Window manually.
But can not load the registers still
I have checked Reset and SYNC_IO pins of master also where they are both low logic during operation.
But CSB is 3.3 V
PS0, PS1,PS2 pins are low
PLL Lock & Slave PLL Lock pins are low.
SCLK pin is 3.3V
But SDIO and SDO pins are both 2.38 V where it seems they are floating, right ?
When you are going to look at the at page 5 of the AD9656 datasheet, you would find the voltage thresholds on the digital logic. In the SDIO pin the VIH is 2.0V, so it is considered as a high logic if it acts as an input.
Another thing that I could add is to check if there is a clock signal present at the SYNC_OUT pin. If there is a signal present in there then that means that your clock signal was properly distributed to the DDS device.
I think the problem is we do not observe clock signal at Sync-Out pin.
What to do now ?
My initial speculation is that the part is experiencing trouble in the REFCLK input. Just for the sake of troubleshooting, can you have your signal coming from a signal source and see if you could detect a signal coming from the SYNC_OUT. If that is the case then the clock signal going into the REFCLK may be out of specification.
We have worked DDS eval board:)
and designed our own DSP+DDS board
We are using fractional divider loop, sweep mod (Ps0)
Everything is OK now. Our sweep period is 1 ms now.
We want to speed up sweep frequency (100 us period).
We can not reach that sweep freq. How can we speed up our sweep freq ?
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