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SC58x: How to share external DDR memories between core0, core1 and core2?

Question asked by Jhon on Dec 31, 2016
Latest reply on Jun 21, 2018 by walkercc

I'm using CCES2.4.0, and created a multicore project for ADSP-SC584.

In the Core1 -> system.svc -> Startup Code/LDF ->External memory, there is a setup:

    Use external memory (SDRAM)

I think if this option is checked, the compiler will allocate external DDR2 (or DDR3) memory to the static variables and dynamic arrays. If not, the external memories can be accessed by pointers or DMA.

 

But in Core0, there is no such thing like LDF file, it seems that the arm core can't know the size of the external memory.

So, how to configure the DDR memoris in core0?

 

And furthermore, how to share the DDR momories between the 3 cores?

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