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free run line length register in cp mode

Question asked by *** on Dec 31, 2016
Latest reply on Jan 2, 2017 by JeyasudhaMuthuPerumal

hi,i am using adv7441a for component video processing.the data rate is 13.5 mhz .i require the cp output clock to be twice the data rate(llc o/p should be 27mhz)..in hardware manual as per section 12.1.1 its given LLC_PAD_SEL_MAN=1 and LLC_PAD_SEL[2:0]=111.but when  i write these values in 8f register.the output clock is not locking properly.the llc o/p is varying from 26mhz to 52mhz. . the input and output standard is 625i.i am writing all the values as per the design document.

 

625i YPrPb In 4X1 16Bit 422 Out through (Encoder in 625i HS & VS Mode):
42 03 0C ; Disable TOD
42 05 00 ; Prim_Mode =000b for SD-M
42 06 0b ; VID_STD=1011b for SD 4x1 525i
42 1D 40 ; Disable TRI_LLC
42 3C A8 ; SOG Sync level for atenuated sync, PLL Qpump to default
42 47 0A ; Enable Automatic PLL_Qpump and VCO Range
42 6B D3 ; Select 422 16 bit YPrPb out from CP.656 Enabled
42 7B 1C ; Disable AV Codes
42 85 19 ; Turn off SSPD and force SOY. For Eval Board.
42 8F 70 ; Turn on LLC_PAD_SEL.
42 BA A0 ; Enable HDMI and Analog in
42 F3 07 ; Enable Anti Alias Filters on ADC 0,1,2

 

thank you

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