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tllc lock issue in cp mode

Question asked by *** on Dec 30, 2016
Latest reply on Jan 2, 2017 by JeyasudhaMuthuPerumal

hi,

i am using adv7441a in my project.my input standard is 625i( 20 bit o/p).i am writing all the registers as per the evaluation document.

42 03 0C ; Disable TOD
42 05 00 ; Prim_Mode =000b for S-M
42 06 0B ; VID_STD=1011b for SD 4x1 625i
42 1D 40 ; Disable TRI_LLC
42 3C A8 ; SOG Sync level for atenuated sync, PLL Qpump to default
42 47 0A ; Enable Automatic PLL_Qpump and VCO Range
42 6B D1 ; Select 422 10 bit YPrPb out from CP. 656 Enabled
42 7B 04 ; Disable AV Codes
42 85 19 ; Turn off SSPD and force SOY. For Eval Board.
42 BA A0 ; Enable HDMI and Analog in
42 C9 0C ; Enable DDR Mode
42 F3 07 ; Enable Anti Alias Filters on ADC 0,1,2

 

but if i disable the tod(42 03 0C) the status 2 reg  reads 0x0c (pll is not locked).i am following the same sequence as given.is there any other reg which has to be written.

 

thank you

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