We are using AD9364 for one of our project as a transceiver for RF path.
AD9364 in CMOS mode . In our receiver RF path external LNA also there along with AD9364 to get more receiver sensitivity . We are running 9364 in manual gain mode.External AGC is there to control the gain in receiver path. This VGA gain will be controlled from the FPGA based on RF RSSI signal in receiver path. The corresponding signal will be given to AD9364 receiver. Input to the receiver is burst packet signal. Whenever packet starts FPGA starts reading the RSSI and based on RSSI , AGC will be applied correspondingly. Initially VGA in high gain. When ever strong signal comes to the receiver AGC will be applied and VGA gain will be go down suddenly.For these gain changes and change in the input signal level to the AD9364 , Rx I, Rx Q samples of 9364 DC offset is changing. Please refer the captured chip-scope signal,where Circled area is maximum gain signal to 9364 and squared area path is after AGC is applied. If the external gain changes are less then the DC offset shift is less. Please refer another attachment for this small change.
As per AD9364 ,it will correct DC offset calibration at initialisation only.And we are not changing the receiver gain also.
Is there any way in 9364 configuration or interface to correct this DC offset shift.