I would like to integrate custom modem IP on the FMCOMMS2 Reference Design (Zed). Essentially, this modem will accept bits from the software domain, produced modulated samples for consumption by the AD9361 unpack/fifo/controller. On the receive side, it will receive samples from the AD9361 controller->fifo->pack modules, and produce bits. I have a few questions about how to do this:
- My hope with this scheme is to use the existing gr-iio driver to move data to the software/application layer
- I was planning to "splice" the modem between the DMA->UNPACK interface, and the demodulator between the PACK->DMA interface. I chose this location because it provides aligned I/Q samples for simple consumption/production by my modem. Does this seem reasonable?
- I do not require any concept of framing throughout the receive chain, as this is a continuous streaming application. In this case, I don't understand what to to with the demod_sync signal on the ADC_PACK module. Does the DMA controller still require this?
- Can someone provide timing diagrams of the adc_valid, adc_sync, adc_data, and adc_clk signals or a textual description of their behavior? Likewise for the relevant dac_dma signals - dac_clk, dac_valid, dac_data, etc.
- On transmit, can I rely on dac_valid as a means of back-pressure? It won't assert unless the downstream FIFO's are prepared to consume data from the DMA controller?
There will be more question, I'm sure.