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How to receive and 'display' ACK bit on FPGA?

Question asked by techn-fecp on Dec 27, 2016
Latest reply on Feb 23, 2017 by mattp

I have been stuck at this problem for the past week.I am using multiple SRLs (Shift Registers) to set up I2C comm. at around 56 Khz with the ADV7171.I need the I2C to configure the ADV7171 encoder on startup.From what I understand, an effective way to confirm successful I2C communication would be to receive the ACK bit (when the SLAVE pulls the device low) and use it to confirm that the preceding byte write has been acknowledged.This is something I've been unable to do and would like help with.

I am attaching the code and would be extremely grateful if someone could have a look, and am also attaching pictures of START and STOP (I2C conditons) that I have simulated.

I have been stuck for the past week and can't proceed without verifying I2C.

Thank you!