Hello, I would like to confirm about relationship between BUSY, INHIBIT, RIPPLE CLK behave.
1) During /INHIBIT is kept low, DB1-16 pins state are held even RIPPLE CLK happen?
2) When both "counter change timing from 0x00FF to 0x0100" and "put low /INHIBIT timing" are happen same time, is there any possibility output data conflict?
3) BUSY will generate by /INHIBIT goes to high within 70~140ns, but the customer observe if RIPPLE CLK generate after /INHIBIT high, BUSY signal timing goes to delay. So my understanding if RIPPLE CLK happen, then BUSY timing will be count from RIPPLE CLK timing not /INHIBIT goes to high timing. Is it correct?
4) with regard 3) , I would like to make sure BUSY definitely is generated by /INHIBIT high regardless RIPPLE CLK.
Thank you for your help in advance.