My customer have tested the clock performance of AD9528 using AD9528 evaluation board as the below conditions.
- REF : 122.88MHz / External VCO : 122.88MHz / PFD : PLL1-30.72MHz, PLL2-122.88MHz
the following data is 3.84MHz clock output on AD9528 using sysref gen block
Unwanted spurious signals are observed.
The following other data is 3.84MHz clock output on AD9528 using PLL2 output clock.
The performance of the clock is good.
My customer want to make the clock output using sysref gen block equal to the clock output using PLL2.
Is it possible ?
Please advice the customer about the cause and solution of the above symptom.
Thanks in advance.