Just a comment, maybe a way to improve things in the new year. I had a customer recently who was working with the FPGA design documents that we provide to design a JESD interface for one of our high speed ADCs. He was able to get things working and was happy in the end, but suggested that, specifically in the FPGA code blocks, that we add more comments and a little more description on exactly what was going on. He told me that it would have saved him a good deal of time if he didn't need to spend so much time decoding our FPGA blocks. This customer is a very sharp guy, to his credit he was able to get his interface working.
take care all!