We are using an external 625KHz clock to drive the AD7124-4 modulator in high power mode. We see that the CLK_SEL bits in the ADC_CONTROL_REGISTER should be set to 0b10 for an external clock, and that's what we're using. However, there is an CLK_SEL option for a clock divide by four (0b11) that implies we could use in a 2.5MHz external clock on the CLK pin. We can put in a 2.5MHz clock but what is the point? Is there an advantage if we use a 2.5MHz clock divided by four?