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AD7124-4

Question asked by slastuka on Dec 22, 2016
Latest reply on Mar 5, 2017 by JellenieR

We are using an external 625KHz clock to drive the AD7124-4 modulator in high power mode.  We see that the CLK_SEL bits in the ADC_CONTROL_REGISTER should be set to 0b10 for an external clock, and that's what we're using.  However, there is an CLK_SEL option for a clock divide by four (0b11) that implies we could use in a 2.5MHz external clock on the CLK pin.  We can put in a 2.5MHz clock but what is the point?  Is there an advantage if we use a 2.5MHz clock divided by four? 

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