I want to add DUC/DDC compiler ip in AD9371 Transmitter path reference design.
I wish to insert this DUC block between DMA and axi_ad9371_core blocks. So I can transmit 10 MHz LTE TM3.1 Mode signal and verify whether AD9371 support LTE signals bandwidth.
But as the axi_ad9371_core IP, each channel component, such as dac_data_i0[31:0], has a 32 bit width.
The axi_ad9371_core take two consecutive samples at a time for I component only (32 bits).
But DUC IP core take only one sample of 16 bits.
Please suggest How to split this 32 bits into 16 bits continuous samples?