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Large DC Offset

Question asked by nadavb on Dec 21, 2016
Latest reply on Jan 4, 2017 by sripad

Hey all

I published a question about a week ago. You can see it at the bottom of this message

Shortly, I asked about a large DC offset that appeared in TDD mode at the receiver 

It seems that changing the value the 5 LSBs of register 0x190 from 0xF to 0xA solved the problem

This register is described in the "register map" file as controlling the loop gain attenuation of the BBDC tracking algorithm

Can anyone provide some details about the BBDC tracking algorithm with emphasis on what register 0x190 does and how to determine its value?


############# Old Question #############

I am working with the AD9361 in TDD mode with 0x13=1

the AD9361 is connected with freescale's bsc9131

I have a proprietary waveform with TTI=2msec

To implement the TDD I am using SPI commands to control the ENSM with register 0x14

when I toggle between the TX and RX modes at the subframe rate - i.e. every 2msec I change the ENSM state - then I have a large DC offset at the receiver. 

I am attaching an image of white noise received by Rx1 and Rx2. and the offset is apparent (full sacle is +-2048)

I am working with MGC with max gain of 71dB. when I the ENSM is in RX state and does not transition to TX state at all then the offset disappears

I tried to change registers 0x170-0x182, 0x185-0x194 and 0x19a-0x1A5, but I didn't get an improvement

Please advise


Thank you