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Communication b/w ARM L2 Cache and SHARC core in ADSP-SC57x

Question asked by MZC on Dec 21, 2016
Latest reply on Jan 13, 2017 by Harshit.Gaharwar


I have few questions.

1. Is there any architecture difference between ADSP-SC57x and ADSP-SC58x in terms of data transfer from ARM L2 cache to SHARC core? It seems to me for ADSP-SC57x, Master port of SHARC can be directly connected to Slave port of L2 Cache without system crossbar. Is it correct assumption?

2. How SHARC core access system memory via ARM L2 cache in ADSP-SC57x? Any code snippet will be helpful.

3. On page 8 of DataSheet ADSP-SC57x, the Memory Map figure 5 have some duplicate address for L2 BOOT ROM1 and ROM2. Can you send me the correct Figure?

4. I assumed FIR Accelerator on ADSP-SC57x and ADSP-SC58x are same. Since FIR throughput formula is different in both manuals, Can you verify formula for both chips?






Mussab Zubair