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ICE-100B  connecting to custom board with 5 Blackfin DSP

Question asked by pschei on Dec 20, 2016
Latest reply on Feb 27, 2017 by Kader.M

I'm trying to use an ICE-100B with a custom board which has  4x BF609s and and 1x BF561 in the JTAG chain. The processors each boot from their own SPI flash chips (Winbond W25Q32), and I have been able to program these with an external  eprom programmer and successfully  boot the processors with an appropriate test program (each just flashes an LED).


However from CCES (v1.2) I can't seem to load or debug any code via the JTAG interface. It seems that I can't have a debug configuration with more than one type of Blackfin in it so I created a configuration with the 4x BF609 and 2x "Unknown" devices with an IR width of 5 (Yes! the BF561 appears as two JTAG devices both on my board and on the BF561-EZ evaluation board). When I run the configuration test utility it says 6 devices detected and it will run indefinitely in continuous scan mode, so I guess data is being clocked in and out OK.


When I try to load a program into one of the BF609 (ignoring the rest in the chain) it seems to halt the first two BF609 in the chain (i.e. the test program booted from SPI flash stops running) and then it sits there for a while and eventually reports back "failed to halt processor 2". This happens regardless of which processor I try to load the code into, almost like it is trying to halt all of the processors, but just times out.


If I change the configuration to have just one BF609 as the first in the JTAG chain and make the rest "Unknown" with IR width of 5 then it always comes up with "unable to connect to processor". In this case I was sort of expecting it to just ignore the "unknown" devices and leave them in BYPASS but it looks like it is auto detecting them (it sometimes draws a little text/graphic of the JTAG chain labeling *all* of them as BF609 and BF561 rather than as unknown). I think that it then assumes that the SDU has enable the JTAG TAP for each core so that the Instruction Register width is 15 rather than 5 (i.e. as it would be in BYPASS) so then the bits clocked out of the chain no longer make any sense.  


I have tried the ICE-100B with UrJTAG on a Linux machine and can read the IDCODE registers for each processor and seem to be able to change the instruction in the IR but it is a bit of a steep learning curve to work out if I can actually load and debug code with gdb and something like gdbproxy.


Any ideas if it is possible to use ICE-100B to debug a board like this. Anybody done something similar?