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AD9361 DCXO tuning issue

Question asked by Usher on Dec 20, 2016
Latest reply on Jan 4, 2017 by Usher

Hello ADI people,


   I perfomed DCXO tuning on AD9361 with AD-FMCOMMS3-EBZ but observed one phenomenon which caused concern to me. The concern is that how long the whole CLK chain takes to be re-stabled after changing DCXO value? Below is my configurations, testing flow and testing result for your reference before you answer my question.


   The CLK_OUT of AD9361 is monitored for DCXO calibration, and the CLK_OUT is set to be 7.68MHz in my case. I try to change value of Register 0x292 to 0x294 to get an accurate 7.68MHz CLK_OUT on spectrum. However, the phase noise of 7.68MHz became really bad when every time I changed those registers. Phase noise of 7.68MHz came back to a good level after a while. Following two picture are screen shots of spectrum, you guys can see huge difference on phase noise.   


   I thought the reason of poor phase noise is that whole CLK chain needs time to re-sync (or re-lock) one by one. All way down from external crystal, BBPLL reference clock block to BBPLL itself. If that's real, there must to has an un-operating period for DCXO tuning. But I need to know how long it takes; us, couple ms or even longer?


Final, thanks for your support in advance.