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FMCDAQ2 - ADC 5Gbps operation

Question asked by frankella on Dec 20, 2016
Latest reply on Jan 13, 2017 by rejeesh



I am trying to reduce the sample lane rate of FMCDAQ2 - AD9680 to 5Gbps.  The provided design works in full BW mode and it uses 4 lanes 10Gbps each.


My goal is to set the decimation to 2 and operate lanes 4x5Gbps.


So I have two things to do.

1) Program AD9680 for decimation by two at 1GSps

2) Modify the GT core settings and recompile the FPGA code.



1) In ad9680.c,  ad9680_setup() I commented one line and added commands to place an HB Filter in-line.




//ad9680_spi_write(slave_select, AD9680_REG_CHIP_DEC_RATIO, 0x00);// full sample rate (decimation = 1)



/* Modified for 5Gbps operation */


ad9680_spi_write(slave_select, AD9680_REG_CHIP_APP_MODE, 0x01);      // DDC0 ON

ad9680_spi_write(slave_select, AD9680_REG_CHIP_DEC_RATIO, 0x01);     // (decimation = 2)

ad9680_spi_write(slave_select, AD9680_REG_JESD_LANE_CONTROL, 0x10); 

ad9680_spi_write(slave_select, AD9680_REG_DDC0_CONTROL, 0x83 );      // DDC0 (complex mixer; 0 dB gain; variable IF; complex outputs; HB1 filter)

ad9680_spi_write(slave_select, AD9680_REG_DDC0_INPUT_SEL, 0x04 );    // (DDC I input = ADC Channel A; DDC Q input = ADC Channel B)


2) Using the Xilinx 7 Series Transceiver Wizard I generated an IP with the following settings. (TX turned off)

                Reference Clock: 500MHz

                Lane Rate      : 5Gbps

                External Data Width : 40

                Internal Data Width : 40


                Looking at the settings from the wizard generated code I modified the axi_daq2_gt. With the following settings.


           Pma Rsv 0-7      0x001E7080

           Rx Cdr Cfg 0-7   0x03000023ff40200020

           Rx Out Div 0-7   2

                The other settings are left as is since they already match the wizard generated one.


                Qpll0 Cfg    "000011010000000000110000001" = 0x680181

                Qpll0 Fbdiv  "0000110000"                  => Div by 20

                Qpll0 Refclk Div 1



The resultant bit file does not work properly. That is:


QPLL0 Locks                  - verified by jesd204b_gt_txrx_status()

The lane Sync achieved - measured the SYNCB pin with oscilloscope

AD9680 is left in the ramp mode and "i_system_wrapper/system_i/axi_ad9680_fifo_dma_wdata[15:0]" data is probed by a debug probe. The received data is not a ramp!



Whereas programming the FPGA with the original ADI bit file but using the same SDK project discussed here uncommenting the original code, commenting the modifed code (described above) in ad9680.c, I can see a ramp.


Is there anything I miss?