I have a question regarding the maximum serial read clock frequency for serial read operation in case the AD7609 is powered with Vdrive=3.3V.
According to the data sheet, this is 15MHz, but with the constraint that the output-data is already valid on the falling edge of SCLK.
The "Data access time after SCLK rising edge" (t19) for 3.3V operation is defined as 26ns. If I use the next rising edge to sample the AD7609's output data into my FPGA, it should be possible to run the serial clock with 33MHz.
33MHz means 30.3ns, so I have 4ns guaranteed setup-time for my FPGA inputs.
Is my understanding of the AD7609's serial interface correct?
Is the "Data access time after SCLK rising edge" the root cause for the serial clock frequency limit?
Assuming my FPGA is able to sample the data with only 4ns setup-time, is it possible to run the AD7609 with 33MHz serial clock frequency?
I am looking forward to your answer.