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ad9361_dig_tune both TX RX tune failed

Question asked by JunSherlock on Dec 19, 2016
Latest reply on Dec 22, 2016 by rejeesh


My design has 3 microblaze CPU, two for running 802.11 protocol, one for run ad9361 (fccomms3) driver


I use the clk_out (40MHz) of the ad9361 as the protocol system clk.


I use the fpga IP core from the below

fpgahdl_xilinx/cf_lib/edk/pcores at master · analogdevicesinc/fpgahdl_xilinx · GitHub 


and I didn't use the axi_dmac. 

I can transmit my data and receive very well


Now my question is, 

I make my own spi IP(in order to run initialization by hardware), but I just don't connect and wire to the design

and the driver initialization failed

(red mark means I add some xil_printf to print information)



the difference is I add a IP into the design but the whole system will not use it and it will not connect to any other IP


the other question is that the timing constraint of ad9361, I think ot might be add to .ucf


can some body teach me how to add?