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Direct Access to L2 memory from SHARC cores

Question asked by YanikM on Dec 18, 2016
Latest reply on Jan 10, 2017 by YanikM

Hello!

I'm trying to implement a simple handshake/sync mechanism between 2 SHARC cores. I defined a structure in C and placed it in L2 memory in both Core1 and Core 2 projects. The code below implements exchanging of 32 bit address between 2 cores. 

 

However, when trying to access this structure from both cores, it doesn't work. 

 

The shared structure looks like this:

typedef struct stShared
{
volatile UInt8_t core_0_addr_ready;   // READY flag of core 0
volatile UInt8_t core_1_addr_ready;  // READY flag of core 1
volatile Float32_t *core_0_data;         //32 bit data of core 0
volatile Float32_t *core_1_data;         // 32 bit data of core 1
}Shared_t;

 

This is a sample of the code:

 

// p_L2_shared is a pointer to "Shared_t" memory structure

Float32_t * volatile * volatile p_loc_data;   /* Pointer to local data (this core) */
Float32_t * volatile * volatile p_rem_data;   /* Pointer to remote data (other core) */
volatile UInt8_t *p_loc_flag;    /* Pointer to local flag (this core) */
volatile UInt8_t *p_rem_flag;    /* Pointer to local flag (this core) */

if( 0 == core_id)
{
/* Runs in SHARC Core 0 */
    p_loc_data = &(p_L2_shared->core_0_data);
    p_rem_data = &(p_L2_shared->core_1_data);
    p_loc_flag = &p_L2_shared->core_0_addr_ready;
    p_rem_flag = &p_L2_shared->core_1_addr_ready;

    data = (UInt32_t)<some 32 bit address>;
}
else
{
    /* Runs in SHARC  Core 1 */
    p_loc_data = &(p_L2_shared->core_1_data);
    p_rem_data = &(p_L2_shared->core_0_data);
    p_loc_flag = &p_L2_shared->core_1_addr_ready;
    p_rem_flag = &p_L2_shared->core_0_addr_ready;
    data = (UInt32_t)<some 32 bit address>;
  }


p_data = (void *)data;
/*
* Write local data to shared structure - each core writes a 32 bit data and sets its flag
*/


*pAnrCommState->p_loc_data = (Float32_t*)p_data; /*p_tx_data;*/
*pAnrCommState->p_loc_flag = DATA_READY;
/* Wait if remote flag is still not set! */
while(*pAnrCommState->p_rem_flag != DATA_READY);

*pAnrCommState->p_rem_flag = DATA_RESET;

 

When I run it, both cores stuck in last while loop (line 37), but i also see that core 0 didn't perform the data writes (line 34-35). Core 1 DID succeed the write. I'm guessing it has to do with simultaneous access of 2 cores to the same memory area. Am I correct? 

 

 Is there anything i need to configure or control so that shared access to this structure may be possible? Is it possible to monitor some register for the core to know it can access L2?

Thank you!

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