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AD9361 Questions

Question asked by hplee on Dec 16, 2016
Latest reply on Dec 19, 2016 by sripad

AD9361 Questions

Q1:

The setup I have is a direct rebroadcast (de-serialiser (DDR->SDR) followed by serialiser (SDR->DDR)) in the FPGA at a clock speed of 245.76MHz (sampling rate of 122.88MHz). This one is running using the baremetal no-OS with modifications to the architecture to achieve the direct rebroadcast. (FDD mode on LVDS). The spectrum from the TX side is fed into a spectrum analyser.

 

The Linux OS version is as is, without modifications in the SD card, and booted directly from there.

 

Observations are done at 200MHz LO, with a 205MHz sine tone generated from a signal generator (low frequency chosen to ensure low losses) and same RF gain on the input without observing spurs due to clipping (and 0dB TX attenuation for the rebroadcast setup), 30kHz RBW, averaging over 16 measurements.

  • The Linux OS does not allow a sampling rate of above 61.44MHz. The noise floor measured using the Linux OS “spectrum analyser” and has a “sinusoidal pattern” across the frequencies, with a maximum of around -109.8dBm/Hz at maximum and -119dBm/Hz at minimum. The received signal is -9.25dBm with RF gain of 15.
  • In my baremetal setup, the noise floor is different when I use decimation RHB1/RHB2 (Register 0x003 set to 0x44) vs without (set to 0x40) and also note that the clock speed changes. Without decimation I am getting a flat noise floor of -91.8dBm/Hz while with decimation, I get an M-shaped noise floor (with the lowest in the centre LO frequency) and the highest towards the sides with -124.8dBm/Hz in the middle, and -99.8dBm/Hz at the “peaks” of the “M”. The received signal is -6.3dBm with the same RF gain of 15.
  • Changing the RF gain does not affect the noise floor of the baremetal setup, but it does affect the noise floor of the Linux OS setup. I suspect the noise source is not in the RF chain.

 

I am unable to explain the high noise floor relative to what the Linux OS is managing to achieve.

 

Q2:

I would also like to know how to receive the IQ data from the internal TX monitor. (Power monitoring, TPM is not a concern)

From the current configuration (1R1T FDD LVDS), I write via SPI to the registers in the following order:

[0x14] = 0x00 // transit ENSM to wait state

[0x13] = 0x00 // change to TDD mode

[0x57] = 0x30 // power up Tx1 monitor LO

[0x6E] = 0x21 // Tx1 monitor enable

[0x67] = 0x20 // enable DC offset tracking for Tx monitor. Set gain to 0dB

[0x68] = 0x00 // set gain to 0dB

[0x70] = 0xC1 // set TIA gain to 0dB

[0x01] = 0x20 // enable Tx1 monitor path

[0x14] = 0x04 // transit ENSM to alert state

[0x14] = 0xA0 // transit ENSM to transmitting state with RX data port enabled (reference manual says IQ data will be present here)

 

However, after doing so, while the transmit waveform comes out fine, and I can read RSSI power on the TX power monitor ([0x6B] gives results), there is no IQ data present on the RX data port. The port stays silent (signal lines are all static).

 

Any ideas as to why the AD9361 isn’t putting data on the RX port?

 

 

Please advise.

 

 

Thank you.

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