I am currently working on a design problem where I need to generate a wide-band signal that is larger than the 56 MHz of TX bandwidth provided by the AD9361. I have heard that the locking time of the LO is estimated to be a maximum of about 20 microseconds, but my question is in regards to the timing of the LO switching. Can the switching of the LO be timed with the signal timing to ensure that the same pattern is transmitted at each center frequency the LO frequency is set to? Also, if the frequency change is fixed, say 50 MHz increments, how stable is the LO lock time?
The second question I have is, based on this SDR setup, what is the best way to code this system? I have been programming the signal I am trying to repeat at different carriers through the FPGA's DDS via MATLAB code and am trying to simply switch the LO center frequency, but the MATLAB implementation of this process is faulty, and it is difficult to standardize the timing of the transitions. Would I most likely need to communicate with the FPGA on the ZedBoard directly, or is there a better setup, for instance C code, that would allow me to switch the LO and time the switch such that one full period of the signal is transmitted before switching so that the same signal appears at each LO frequency?
It would be a bonus if the RX LO could be switched simultaneously so the signal could be recovered.