We have several ADAU1761 devices each connected with individual SPI busses to an FPGA which is doing the configurations. The FPGA has the ability to trigger writes and reads to each individual 1761 devices and having monitored the actual busses using a logic analyser the SPI clocks and CLATCH lines are functioning to spec. However when we read back register values sometimes the first bit of the returned data or the first two bits disappears. We've been using 4012h as a test location into which we deliberately set C3. When we perform a single read of this location it typically returns 03h or sometimes 43h, and even once 83h. However if we read 4011h followed fairly soon by 4012h then we get the correct C3h returned. My initial assumption was that we needed pull-up resistors on the lines (your datasheet specifies 2K on the lines when used in I2C mode but nothing in SPI mode). Fitting pull-ups made no difference and all codecs are behaving the same. Component batch fault?
Is there a known bug here or are we not allowed to read back registers in some fashion? We are primarily doing these reads to debug the configuration process but clearly I can't trust what I'm reading back to get very far.