I am using the KC705 reference design with the AD9467 FMC. I have modded the AD9467 to use the AD9517 as the internal clock source and have configured the AD9517 to generate 128 MHz clock via spi/microblaze. The default Vivado constraint (adc_clk) in the KC705 reference design is 4 ns (250 MHz) for maximum performance. I have custom processing logic that I only want to constrain to 128 MHz. Can I change the constraint on adc_clk in Vivado to something closer to 128 MHz? Will the interface to the AD9467 work, or does it depend on having adc_clk constrained to the higher rate (4 ns)?