When we run the make system to build the ADRV 9371 project, we always get a clean timing result. Yet this is not reproducible using the GUI? We are using Vivado 2015.4.2.
Using the Gui we get a ton of setup timing errors... with the worse case setup slack of -2.347. This negative slack time belong to this path with some detail here:
Start Point Pin : up_xfer_data_reg/C
End Point Pin: d_data_ctrl_reg/D
Start Point Clock: clk_fpga_0
End Point Clock: mmcm_clk_0_s
Start Point Pin Primitive: FDCE/C
End point Pin Primitive : FDCE/D
High Fan-out: 1
Cumulative Fan-out: 1
Path Delay: 1.765
Logic delay: 0.223
Net Delay: 1.542
Clock Skew:- 0.277
Requirement Path Type: 0.204
What are we missing? Is there some type of ordering of the constraints that behaves different in GUI, yet is better controlled via the make scripts?
any suggestion would be appreciated.