Using zc702, fmcomms5, version 2015 R2
We regenerated the FPGA build using Vivado 2015.2.1, ported the hardware into the SDK, following the instructions on the ADC wiki page (link).
We're having a problem where the FSBL that is generated is much bigger than the FSBL from the reference image that we downloaded, where the reference fsbl.elf is 240K (found in bootgen_sysfiles.tgz), and the file that we generated from the SDK is 417K.
- When we boot using a BOOT.bin generated with our bitstream file, our fsbl.elf, and the reference u-boot.elf, we get video distortion on the monitor.
- When we boot using a BOOT.bin generated with our bitstream file, the reference fsbl.elf, and the reference u-boot.elf, it works as expected.
The extra large fsbl.elf is generated using both Linux and Windows tools.
Does anyone have any insight on this?