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adv7610 tdms pll

Question asked by ssa_eos on Dec 13, 2016
Latest reply on Dec 13, 2016 by GuenterL

Hi, Matt

I have a question regrading TMDS PLL,

There are some registers in HDMI section initialized as mentioned in the script:

68 8D 04 ; LFG
68 8E 1E ; HFG

 

But register EQ_DYN_EN 0x96 keeps default value 0x00 which means ". The equalizer is configured in static mode"

 

Does it mean that "static mode" is controlled by registers 0x8D and 0x8E that define LFG and HFG?

What is the range for those registers?

I have a problem when PLL does not lock for some sources and I'd like to play with those registers.

Thank you.

Sergey

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