My custom IP core that is located between AD9361 core and DMA gathers all the incoming RX data, but it's output to dma happens rarely, only when I make a request from Linux.
By default, libiio is configured to acquire data continously, without any losses, but this way I get many buffers full of zeros instead of one buffer with my data.
Is there any way to tell libiio start acquisition only when I tell it so? I thought that previous slow interface could help, is it so?
Also I tried to simply disable the valid signal to DMA core in PL while I have no data for output. This way, will the buffer filling in linux kernel stop and wait until data is once again provided to the DMA? I understand that this is a non-standart behaviour for the system, but maybe you could tell me what the reactions of the DMA driver and libiio would be, if there is no input data to DMA (not zeros, but really no data, the counter in DMA IP is not increasing at that moment)? If needed, I can post a similar question in the FPGA section.
Thanks in advance.