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AD5040

Question asked by hejialiner on Dec 11, 2016
Latest reply on Dec 20, 2016 by hejialiner

device: AD5040

question: only the low 7 bit can be used. the data must be less than 0X007F.if exceed this number,the decive don't have votage output.the following is my verilog code.

 

in the accessary, there are simulation result,datasheet (chinese and english)

 

module AD5040test(
input i_clk,
input ni_rst,
output da_sync,
output da_din,
output da_sclk
);


oddr2_clk oddr2_clk_20m_0 (
.po_clk(da_sclk),
.i_clk(i_clk),
.ni_clk(~i_clk)
);

reg nr_rst;
reg r_dejitter;
always@(posedge i_clk) begin
if(!ni_rst) begin
{nr_rst,r_dejitter} <= {r_dejitter,1'b0};
end
else begin
{nr_rst,r_dejitter} <= 2'b11;
end
end

//I路
reg r_buf_sync;
reg[15:0] r_buf_din;
reg[7:0] r_da_cnt;
reg r_da_cnted;
reg rst;
reg r_out_din;

always @(posedge i_clk or negedge nr_rst) begin
if (!nr_rst) begin
r_buf_din <= 16'b0000_0000_0000_0000;
r_buf_sync <= 1;
r_da_cnt <= 0;
r_out_din <= 0;
end
else begin
if(r_da_cnt < 16)begin
r_out_din <= r_buf_din[15 - r_da_cnt];
r_buf_sync <= 0;
r_da_cnt <= r_da_cnt + 1;

end
else begin
if (r_da_cnt < 24) begin
r_out_din <= 0;
r_buf_sync <= 0;
r_da_cnt <= r_da_cnt + 1;

end
else begin
r_buf_sync <= 1;
r_out_din <= 0;
r_da_cnt <= 0;
r_buf_din <= 16'b0000_0000_0101_0011;

end
end
end
end
assign da_sync = r_buf_sync ;
assign da_din = r_out_din ;

endmodule

Outcomes