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ADV8005 Tx Init

Question asked by qwerty78 on Dec 9, 2016
Latest reply on Dec 14, 2016 by JeyasudhaMuthuPerumal

I've looking at the initialization sequence in the EVAL-8005 driver software and some of the registers modified don't appear in the user manuals (either software or hardware).  Additionally, the comments indicate that the register writes are ADI recommended, but I can't find any references to that recommendation.  I've included the section of code, could you clarify where these recommendations come from?

 

  *===========================================================
* Init TX section of 8005, from 176.4kHz_PCM_AES3_2Ch_Audio
*===========================================================*/
CONSTANT UCHAR TxInitTable[] =
{
0xEC, 0x41, 0x10, /* Power up all circuits */
0xEC, 0x41, 0x10, /* Power up all circuits again */
0xEC, 0x01, 0x00, /* N[19:0],Set N Value(4096) used for Audio 176.4KHz */
0xEC, 0x02, 0x62, /* N[19:0],Set N Value(4096) used for Audio 176.4KHz */
0xEC, 0x03, 0x00, /* N[19:0],Set N Value(4096) used for Audio 176.4KHz */
0xEC, 0x0C, 0xBF, /* Enable AES3 Audio Mode */
0xEC, 0x13, 0xFF, /* CS Category code - not defined - 111 XXXXL */
0xEC, 0x15, 0xC0, /* CS I2S Fs - I2S_SF[3:0] - 1100b - Fs = 176.4KHz, VFE_input_id[3:0] - 0000b = 24-bit, 444 YPrPb/RGB input separate syncs */
0xEC, 0x16, 0x61, /* VFE_out_fmt[1:0] = 01b - YCrCb 444 output,VFE_width[1:0] = 10b - 12 bit per ch, Input Style 00b, VFE_input_cs = 1b - YCrCb input */
0xEC, 0x40, 0x80, /* GC_pkt_en = 1b,General Control packet enable */
0xEC, 0x4C, 0x06, /* GC_CD[3:0] = 0110b - 36 bits per pixel Output */
0xEC, 0x55, 0x40, /* Y1Y0[1:0] - 10b - Set YCrCb 444 in AVinfo Frame */
0xEC, 0x56, 0x08, /* R[3:0] = 1000b - Set active format Aspect - same as aspect ratio */
0xEC, 0x96, 0x20, /* HPD_INT = 0b HPD Interrupt clear VSYNC_INT = 1b - Vsync interrupt active */
0xEC, 0xAB, 0x38, /* hdcp_start_delay = 7 (200ms delay) to pass 1B-05/3B-05 test */
0xEC, 0xAF, 0x04, /* HDCP & Frame Encryption disabled, DVI by default */
/* 0xEC, 0xAF, 0x96, HDMI_MODE_SEL = 1b - Set HDMI Mode (DVI by default) */
0xEC, 0xBA, 0x70, /* No delay for input video clock, use internal EEPROM */
0xEC, 0xD0, 0x44, /* Adjust VCO swing ref to 1.67xBgvref */
0xEC, 0xD1, 0x3C, /* set pllfilt R1=11.5k, C1=50pF, C2=20pF */
0xEC, 0xD3, 0x07, /* Charge Pump (CP) control, off during force filter state, CP=60uA */
0xEC, 0xD6, 0x02, /* Bandoffset_AG, adds offset to VCO curves */
0xEC, 0xDB, 0x0B, /* tuning KVCO for Gear */
0xEC, 0xE0, 0x90, /* A,B,C,D trip points based on AVDDQ, auto starts over the A D trip points */
0xEC, 0xE1, 0xFC, /* normal bias Current for Gear 0 */
0xEC, 0xE3, 0xD0, /* use analog lock filter, 1ms wait for PLL to settle at one gear */
0xEC, 0xE8, 0xE0, /* soft_turn_on=Enabled, tmds clk_en=Disabled */
0xEC, 0xEA, 0x1D, /* set clock op level, clkDRV_level = 500mV, enable cross_coupled inverter for duty cycle */
0xEC, 0xED, 0x40, /* Current for CH2-for TMDS level compliance */
0xEC, 0xEE, 0x40, /* Current for CH1-for TMDS level compliance */
0xEC, 0xEF, 0x41, /* Current for CH0-for TMDS level compliance */
0xEC, 0xF3, 0x01, /* PLL external */
0xEC, 0xF5, 0xCC, /* BandOffset for HG */
0xEC, 0xF6, 0x08, /* Shifting-up the High Gears */
0xEC, 0xF7, 0xF0, /* set VCO and route input to PLL */
0xEC, 0xDA, 0x40, /* Iptat = 4 */
0xEC, 0xF5, 0xD4, /* BandOffset = 20, to account for the change in Iptat */
0xEC, 0x80, 0x7F, /* default=0x0F, Tx Source Termination OFF, When Sink is limited to max 165MHz $$,Use RSet on the Board, Cross_Couple Inverter On, Enable Data Channel, Clock Channel */
0xEC, 0x81, 0x88, /* Charge Injection Ch0 = 8, Charge Injection Ch1 = 8 */
0xEC, 0x82, 0x88, /* Charge Injection Ch2 = 8, Charge Injection CLK = 8 */
0xEC, 0x83, 0x81, /* default=0x00, ADI Recommended Write, When Sink is limited to max 165MHz $$ Set STerm Resistance to 250ohm, 4500/(3 + Reg[6:2]), STerm I=4.65mA */
0xEC, 0x84, 0x81, /* default=0x00, ADI Recommended Write, When Sink is limited to max 165MHz $$ Set Ch1 STerm Resistance to 250ohm, 4500/(3 + Reg[6:2]), STerm I=4.65mA */
0xEC, 0x85, 0x81, /* default=0x00, ADI Recommended Write, When Sink is limited to max 165MHz $$ Set Ch2 STerm Resistance to 250ohm, 4500/(3 + Reg[6:2]), STerm I=4.65mA */
0xEC, 0x86, 0x81, /* default=0x00, ADI Recommended Write, When Sink is limited to max 165MHz $$ Set CLK STerm Resistance to 250ohm, 4500/(3 + Reg[6:2]), STerm I=4.65mA */
0xEC, 0xFC, 0x55, /* default=0x00, ADI Recommended Write $$ Set isel_cml_rx Bias Currents */
0xEC, 0x41, 0x30, /* default=0x00, ADI Recommended Write $$ Tx Packet Reset */
0xEC, 0x41, 0x10, /* default=0x00, ADI Recommended Write $$ Tx Packet Reset Off, not self clearing */
0xF3, 0x24, 0x40, /* data handoff delay settings */
0xEC, 0xE1, 0xF6, /* ADI Recommended Write $$ iselb_clktree_cml_i2c[2.0] to 011b */
0xEC, 0xF7, 0xFC, /* ADI Recommended Write $$ TX1 vco_res_buf_opt to 1. 375mV. Default value of bit. */
0xEC, 0xFC, 0x35, /* ADI Recommended Write $$ iselb_cml_rx_i2c[2:0] to 011b. */
0xEC, 0xE6, 0x03, /* ADI Recommended Write $$ irefincrease[12.0] set bits 9,8,4,3,0 to 1. */
0xEC, 0xE7, 0x19, /* ADI Recommended Write $$ irefincrease[12.0] set bits 9,8,4,3,0 to 1. */
0xEC, 0xF5, 0x8C, /* ADI Recommended Write $$ Bandoffset_hg to 12dec. */
0x00
};

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