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Fastlock and phase margin and delta fastlock topologies

Question asked by burnbush on Sep 4, 2011
Latest reply on Sep 5, 2011 by burnbush

When using fast lock, I select this feature using the standard method. While the timeout counter is counter supplying full Icp thou an altered loop filter topology.  How do you insure loop satiability (say minimum 30 degrees just for the transistion)


I use active loops filters and increase Icp via the time out counter, without the additional circuitry fastlock circuit. This simplifies the speeding up of the low noise OP_Amp based PLL’s, but I have to watch the phase margin.


Sometimes I use the fastlock output to switch caps that surround the Op Amp for even faster speed up. But this involves switches and more PCB space and only gains me ~ 20 more speed at most.


Well thought I’d hear what the AD gurus might have to say. I wish AD had a bit to switch the bit polarity on the CSR which can result in more improvement for none Op Amp based PLL. The ADF4150 is still needed for low noise at times, thus the continued need for ultra low noise Op Amps.


Input welcome Cheers to all,


Jim Carlini  Microwave-Analog Engineer