Hi, I intend to implement TDD operation in FDD Independent Mode. The above guide tells me to take these two "enough time" into consideration. Can anyone tell me how much exactly are these "time"?
Please refer below post
What is the AD9361 Flush State?
Hi sripad, thanks a lot for your kind reply!
I went to read that post you metioned, which tells all about the FLUSH state in the ENSM. As you can see, I'm using the FDD independent mode, so there won't be any FLUSH states. Are you implying these two "time" are both 384 ADC clock cycles?
Also I'm a bit confused about when to apply these two times.
1. the BBP must allow enough time after enabling the receive chain for the digital filters to flush.
Doest this mean after I pulled the receive chain control signal(ENABLE) high, I have to wait that much time before I can safely receive the RX_FRAME.
2. enough time after sending Tx data for the Tx to finish its transmission before disabling the corresponding signal chain.
Does this mean after the TX_FRAME stops, I have to wait 384 ADC clock cycles before I can safely pull the control signal(TXNRX) down?
Yes your understanding is correct.
HI, sripad. Thanks for your patience. According to this post https://ez.analog.com/thread/39110#127827,tlili says "RX_FRAME is generated by the transceiver so there is no range of delay. It starts as soon as the ENABLE signal is detected (by FB_CLK) and the receiver path enables. About 2 FB_CLK cycles is the maximum delay."
Why did he ignored the 384 ADC clock cycles time?
As there is no flush state in FDD independent mode user needs to allow enough time for zeros to propagate through the digital data paths.
This time depends on latency of data path and also number of FIR taps.
384 ADC clk is when ENSM moves to flush state where clk is higher as explained in What is the AD9361 Flush State? . This is not applicable for FDD independent mode and mainly depends on data path configuration
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