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AD9371+zc706/702 IIO Performance Issues

Question asked by pvan on Dec 6, 2016
Latest reply on Jan 11, 2017 by mhennerich



I am in the process of evaluating the ADI reference design based on this platform, and thought I would start a discussion to gather information on the performance capabilities of this design. My objective has been to determine the throughput ceiling of the DMA->DAC tx path via IIO, with no luck so far.


Some config for my setup:

 - I have adjusted the tx sample rate down as low as possible (61.44 Msps) using the filter wizard (device clock constraint at 122.88)

 - Disabled everything video related to reduce resource contention




 - Running iio_adi_xflow_check on axi-ad9371-tx-hpc shows an underflow message.


 - I have also written a small application similar to ad9361-iiostream which writes a single complex tone to the tx path, using a non-cyclic iio buffer. The samples were preprocessed, so my loop was only performing channel writes and a buffer push. I am also reading underflow (according to register 0x80000088, bit 1). I had also experimented with varying the buffer size - all cases reporting underflow. Observing the resulting signal on a spectrum analyzer confirms what appears as a possible underflow issue (random spurs and some spiking at DC). 


 - From what I can tell, it doesn't appear to be possible for an IIO based application to keep up with the tx chain, even at a reduced sample rate 



Is there anything I am missing or doing incorrectly?