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Configuring ADV7401 for decoding NTSC video

Question asked by shara22 on Dec 6, 2016
Latest reply on Jan 4, 2017 by JeyasudhaMuthuPerumal

Hi all,

i am using below given statements for configuration of ADV7401 using I2C interface.

 i am trying to decode  Component NTSC video format but i am not able to get the vsync which has been generated by ADV7401 is not proper can you guys please check and help me out solving this issue below mentioned list is for recommended register settings.

Write_to_Decoder(slave,0x00,0x04); //0x00,0x0A //Auto-Detect PAL, R on AIN4, B on AIN5, G on AIN6
Write_to_Decoder(slave,0x05,0x01); //0x05,0x01 //Primary Mode of Operation-Component Video
Write_to_Decoder(slave,0x1D,0x47); //Use 27MHz Crystal and llc pin active //0x1D,0x47 //Use 28MHz Crystal
Write_to_Decoder(slave,0x3A,0x11); // PIXEL CLOCK = 13.5 TO 55MHz //0x3A,0x11 //set latch clock settings to 001b, 
Write_to_Decoder(slave,0x3B,0x80); //0x3B,0x80 //Enable External Bias
Write_to_Decoder(slave,0x6B,0xC2); //0x6B,0xC2 //Enable HS output, BLUE=P9-P0;GREEN=P19-P10;RED=P29-P20
Write_to_Decoder(slave,0x85,0x19); //0x85,0x19 //Turn off SSPD and force SOG.
Write_to_Decoder(slave,0x86,0x0B); //0x86,0x0B //Enable stdi_line_count_mode
Write_to_Decoder(slave,0x8A,0xD0); // //0x8A,0xB0 //VCO Range to 01b

Write_to_Decoder(slave,0xC5,0xC1); //0xC5,0xC1 //Clamp averaging - CP_CLAMP_AVG_FACTOR[1-0] = 11b
Write_to_Decoder(slave,0xF3,0x0F); //0xF3,0x0F //Enable Anti-Alias Filter on Channel 1,2,3
Write_to_Decoder(slave,0xF4,0x3F); //0xF4,0x3F //Max Drive Strength
Write_to_Decoder(slave,0xB7,0x12); //0xB7,0x12 //HD_MODE_FOR_CLAMP_GEN DISABLED

 

Configure_Decoder_STANAGC(slave,resol_0,resol_1); //Configure Stanag C as default on both the Decoders

Write_to_Decoder(slave,0x06,0x02); // 0X01 for SD 2X2 525I (I/P) AND 1440X576 (O/P) // 0x06,0x03 VID_STD //625i 4X2 (1440x576)
Write_to_Decoder(slave,0x3C,0x5A); // 31Mhz >PIXEL CLOCK> 22MHz // 0x3C,0x58 //PLL_QPUMP to
Write_to_Decoder(slave,0x8F,0x07); // 0x8F,0x07 //FR_LL
Write_to_Decoder(slave,0x90,0x29); // 0x90,0x29 //FR_LL
Write_to_Decoder(slave,0x7C,0xC0); // 0x7C,0xC0 //NO HSYNC SHIFT

Write_to_Decoder(slave,0x7B,0x1C); //0x7B,0x05 //clears the bits CP_DUP_AV and AV_Blank_EN, AV_CODE_EN
Write_to_Decoder(slave,0x7E,0x00); // 0x7E,0x00 //NO HSYNC SHIFT
Write_to_Decoder(slave,0x73,0x12); // 0x73,0x12 //AGC enabled
Write_to_Decoder(slave,0x8D,0x03); // 0x8D,0x03 //default value
Write_to_Decoder(slave,0x8F,0x70); //
Write_to_Decoder(slave,0x90,0x00); //
Write_to_Decoder(slave,0xF9,0x08); // 0xF9,0x04 //VS mode control 60Hz coast. Limited to 42.75 - 66.25Hz
Write_to_Decoder(slave,0xC3,0x06); // adc0 connected to Ain6, adc1 not connected
Write_to_Decoder(slave,0x6A,0x10); // delay locked loop DLL for phase match
Write_to_Decoder(slave,0x6B,0xC3); // delay locked loop DLL for phase match
Write_to_Decoder(slave,0x6C,0xC5); //0XC5 OFFSET CONTROL ---> OFFSET FOR SIGNAL INPUTTED TO ADV7401
Write_to_Decoder(slave,0x6D,0x68); //0X68 OFFSET CONTROL

 the read back values for register 

B1 = 0x78;

B1,B2 = 38D9 blocl length readback value.

Outcomes