I started working on a board which was delevoped at our institute in the past. It contains a AD9234-500 ADC and a Kintex-7 FPGA.
Now I wanted to read out the ADC data. For this I configured all ADC registers to standard. We are using a sample rate of 468.75 MHz an a periodic SYSREF signal with 19.53125 MHz. With 2 converters and 4 lanes per link I'm getting a seriel lane line rate of 4.6875 Gbps (LMF = 421). Is that right?
I started with the DAQ2 reference design containing the AD9680 which should be compatible to the AD9234 we are using. I removed all the blocks which are used for the DAC and all the Microblaze stuff because I didn't want to use all the software needed for the Microblaze at first. I wanted to observe the ADC data with an ILA. So my design looks like this:
When I'm looking at the data output I just see a 0. At the moment I'm looking at the data output of the util_jesd_gt block. All clocks are set up the right way because there is an existing image which works. So there should be nothing wrong with the hardware or the clocks.
What kind of settings do I need to modify on the axi_jesd_gt block for the given parameters? They are all set to the standard values which are contained in the reference design except of the number of TX lanes. They are set to 0 because I don't need any transmitting part.
The JESD204 block has the following settings:
LMFC Buffer Size: 1024
Lanes per Link: 4
AXI Clock: 100 MHz
Sample SYSREF on: Positive Edge
Default SYSREF: SYSREF Always ON
Default SCR: Scrambling On (due to standard settings of ADC)
Default F: 1
Default K: 32
Default SYSREF required on Re-Sync: SYSREF required (not sure about that)
What do you think? Is it possible to modify the design in that way that it works with the AD9234 at the given conditions?
Thank you for your help in advance!