When clocking the programmable logic array (PLA) with HCLK (core clock) is it possible to trigger the ADC with a "one single HCLK cycle width pulse" generated by PLA and routed to the ADC?
The reason why i am asking for is datasheet chapter "ADC CIRCUIT OVERVIEW" Figure 42 which shows #CONVstart to be kept one ADC-clk cylce low to trigger the ADC. Chapter "PROGRAMMABLE LOGIC ARRAY" states the PLA output can be routed to the "#CONVstart signal". Note that a one cylce PLA pulse is smaller than one ADC-CLK cycle therefore a pulse stretcher would be necessary (although it is working in practice).
I have a second question:
Is there a favourite solution how to implement edge triggered ADC on ADUC7026 (i.e. PLA model)?
Thanks in advance & best regards
Found this link meanwhile:
then go to "Example Circuit". This shows an edge to single HCLK pulse to ADC trigger circuit.
Still open the question about the ADC trigger point (ADC-timing Fig. 42 datasheet) / ADC-Clk and PLA-Core-Clk.