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about AD9361 transceiver

Question asked by KDcy on Dec 5, 2016
Latest reply on Dec 6, 2016 by sripad

Hi,

 

I have several questions regarding the ad9361 :

 

We use the AD9361 in FDD mode, 1R1T, DDR.

1/ How can we handle different data rates for RX and TX ?

Our understanding is that it is done by controlling RX_FRAME according to RX BW and TX_FRAME according to TX BW.

 

2/ For RX datapath calibration (IO_delays programmation), can you precise the polynom used ?

As we plan to implement it in a FPGA, can you precise how to synchronize RX received data and data computed at FPGA level ?

 

3/  For TX datapath calibration, can you precise how to synchronize TX received data and data computed at FPGA level ?

 

Regards,

 

Kevin

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