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AD5363 SPI Interface

Question asked by bdolf on Dec 5, 2016
Latest reply on Dec 7, 2016 by Mike_OBrien

We intend to use this DAC with a DSP which supports only 32-bit serial transfers with a continous SCLK. The AD5363 data sheet says: "If a continuous clock is used, SYNC must be taken high before the 25th falling clock edge. [...] If more than 24 falling clock edges are applied before SYNC is taken high again, the input data becomes corrupted."
Most SPI interfaces would just continue shifting and latch the last 24 bits when SYNC is taken high - is this different with the AD5363 because it says "data becomes corrupted" ?

Many thanks!

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