I am using the HSC-ADC-EVALC board with the AD9653 evaluation board.
I want to add 32M SRAM for deeper capture and provide an external trigger (pulse) for the capture with the eval board, Is that possible?
I'll email you some example HSC-ADC-EVALCZ FPGA code for AD9653 capture that uses the optional SRAM and has example triggered capture code. This code is provided as-is and without guarantee.
Unfortunately the HSC-ADC-EVALEZ does not support 32M capture. In default form it can capture 256k depth. With optional SRAM I believe it is similar to the HSC-ADC-EVALCZ (2 x 2M).
Thank you for your interest in AD9653.
Unfortunately the HSC-ADC-EVALCZ cannot accommodate 32M of SRAM. There are pads for optional SRAM but these are for smaller SRAMs (2 x 2M).
HSC-ADC-EVALCZ does have the hardware capability for an external trigger for capture, but a special FPGA program would be needed.
Thanks a lot for your quick answer!
I found the AD9656 eval board with HSC-ADC-EVALEZ support 32M SRAM and external trigger.
Is it possible to get the FPGA source code from HSC-ADC-EVALEZ High speed adc evaluations boards for customer?（AD9656）
thanks for your help.
Thank you very much for these files.
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