Please let us know when ADUM4135 output will latch to either High or low?
More information is needed to answer this question. Are you asking about a specific operating point that you have encountered, or are you asking if we have observed any latching action in the past?
The ADuM4135, like all ADI parts, have been tested for latch-up during design by forcing current into the pins from external sources. This stimuli is performed and used to characterize the absolute maximum operating parameters of the parts. Operation outside of the absolute maximum values may lead to latch-up conditions within the parts. In the absolute maximum tables, these limits usually show up as limits to the voltages on the pins. The most likely scenario for a latch-up condition due to electrical over stress (EOS) is an internal short from power rails to ground rails, causing overheating of the part. This is usually caused by parasitic SCR structures within ICs. Almost all CMOS ICs are susceptible to this if driven outside of recommended operating points, but there are mitigation techniques performed in the design of the ICs to limit the chances of this.
The default state of the ADuM4135 is to set the output low. This means that if there is some sort of interruption on the primary side, causing the transmission from primary to secondary to be cut off (like a UVLO on the primary side, or EOS on the primary side) the output will be driven low.
The desaturation detection circuitry latches the output low by design if the DESAT pin is brought above 9 V (typical) while the gate drive is driving high. This can be cleared by bringing the nReset pin low then high again.
Please let me know if this answers your question, or if you can clarify the nature of the question a little more.
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