I have a customer using the FMCDAQ2 board with no-OS, He's having trouble getting the JESD link to the DAC working.
His question is below. Is this something we can help with or do we need guidance from Xilinx? Do we have a direct contact at Xilinx who can help?
I have the ADC and FPGA configured to be correctly passing JESD data but I cannot get the DAC to seem to receive JESD data correctly and output it to view with an o-scope. I don’t understand all of the IP in the block diagram in Vivado and I see some unexpected data manipulation (using ILA) on the output of the axi_9144_core block and I have no idea what the axi_jesd_gt block is doing.
I have the base project working fine but our end application is targeting 500 Msps and thus will use lower lane rates (5Gbps JESD) and thus I need to update the configurations. The ADC is much easier than the DAC and I haven’t quite gotten it squared away in the DAC yet.