Hello everyone We have custom transceiver board and AD9523-1 is used to clock ADC,DAC, and PLL+VCO's. When we send clock signal to ADC there is a jitter problem in signal. We use crystek CVSS-950 Model 100 MHz VCXO and we run the AD9523-1 without giving reference clock signal to reference pins. Belowed picture is the spectum analyzer result of clock output port of the AD9523-1 . I reduced to sidelobe of the belowed clock signal reducing the charge pump current. How I reduce the jitter of the signal more (below the noise floor). What should I set the AD9523-1 clock generator to run more proper. 100 MHz cutoff low pass ceramic filter is used output of the VCXO crystal.