Hi, on the AD9913, how much worse should the phase noise be when the PLL is engaged (2x multiplication) vs.
when it is direct fed? In this specific case:
Fref: 90 MHz = sysclk
Fref: 90MHz using PLL=2x, 180 MHz = sysclk
For a FIXED output frequency, would there be a 20*log(2) degradation? That is not clear to me since the output frequency
is actually fixed.
The data sheet does not show this kind of comparison, only residual phase noise for direct fed and absolute
phase noise for PLL=4x.